Variability Driven Gate Sizing for Binning Yield Optimization
نویسندگان
چکیده
منابع مشابه
Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing
Noise, as well as area, delay, and power, is one of the most important concerns in the design of deep submicrometer integrated circuits. Currently existing algorithms do not handle simultaneous switching conditions of signals for noise minimization. In this paper, we model not only physical coupling capacitance, but also simultaneous switching behavior for noise optimization. Based on Lagrangia...
متن کاملEvaluating the Effectiveness of Statistical Gate Sizing for Power Optimization
We evaluate the effectiveness of statistical gate sizing to minimize circuit power. We develop reliable posynomial models for delay and power that are accurate to within 5-10% of 130nm library data. We formulate statistical sizing as a geometric program, accounting for randomness in gate delays. For various ISCAS-85 circuits, statistical sizing at a 99.8% target yield provides 25% power reducti...
متن کاملGate sizing for constrained delay/power/area optimization
Gate sizing has a significant impact on the delay, power dissipation, and area of the final circuit. It consists of choosing for each node of a mapped circuit a gate implementation in the library so that a cost function is optimized under some constraints. For instance, one wants to minimize the power consumption and/or the area of a circuit under some user-defined delay constraints, or to obta...
متن کاملTiming Driven Gate Duplication for Delay Optimization
In the past few years gate duplication has been studied as a strategy for cutset minimization in partitioning problems .This paper addresses the problem of delay optimization by gate duplication. We present an algorithm to solve the gate duplication problem. It traverses the network from primary outputs(PO) to primary in-puts(PI) in topologically sorted order evaluating tuples at the input pins...
متن کاملWire Width Sizing for Delay and Yield Optimization
In this paper, two issues about wire width are investigated. The first one is that “Is the minimum wire width under the minimum wire pitch for a process technology good enough from the perspective of timing performance?” The second is that “Is delay sensitive to wire width variation around the optimal width?” We find that the answer to the first issue is “yes”, whereas the answer to the second ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
سال: 2008
ISSN: 1063-8210
DOI: 10.1109/tvlsi.2008.2000252